1. Technical Field
The present invention relates generally to fault--tolerant memory architectures, and more particularly to a memory system that utilizes on-chip fault recovery to enhance data rates.
2. Background Art
In memory systems, it has been a standard practice to provide some sort of fault recovery technique in order to enhance yield/performance. One of these techniques is redundancy, wherein faulty bit/word lines of cells are replaced with spares. Another of these techniques is ECC, wherein a data word is fetched from memory and corrected using generated syndrome bits that identify faulty bits within the data word. See for example the aforementioned U.S. patent application Ser. No. 479,145 and references cited therein.
Another technique is parity, in which a parity bit is generated for a stored data word and is compared against a stored parity bit corresponding to that word. An example of such a system is shown in U.S. Pat. No. 4,528,666, issued to Cline et al and assigned to Texas Instruments.
Yet other memory systems have sought to combine ECC and parity techniques. Examples of such systems as shown in U.S. Pat. No. 3,568,153 to Kurtz et al and U.S. Pat. No. 3,573,728 to Kolankowsky et al, both of which are assigned to the assignee of the present invention. In both patents, new ECC check bits and parity bits are generated for the data as fetched from the memory. Comparing the stored check bits to those newly generated produces a string of syndrome bits that indicate the location of faulty bits within the data word. The syndromes are also used to correct the generated parity as a function of these faulty data bits, and the corrected parity is provided along with the corrected data word.
In providing optimal fault coverage by combining different error coding techniques (such as ECC and parity), the designer must do everything possible to reduce the area and performance impact as much as possible. In other words, these coding techniques add cost by increasing chip size (the requisite logic circuitry consumes critical chip real estate that could be devoted to arrays) while decreasing performance (the data must pass through this logic before being output to the processor, adding delay directly to the data path). In order to reduce the cost of these error recovery techniques, the designer must minimize their impact by minimizing circuit complexity and reducing data delays. One way of reducing data delays is to provide more data in a given time. Neither of the above patents meet these goals; for example, both add appreciably to data delays because parity is generated and then data corrected as a function of the generated syndromes.